In accordance with features of the invention, the increased wordline voltage generated by the wordline voltage boosting circuit improves read access time and write time of the SRAM. The nand gate 98 has nodes 36 and 74 as input and its output node is high, keeping device off. A SumoBrain Solutions Company. In the first embodiment of the clock, the gate of a first device is connected to a first node through a second device. Boost clock circuit for driving redundant wordlines and sample wordlines.
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An output voltage is generated between a common connecting point of the drains of the first and second MOS-FETs and one potential point of the second voltage supply source.
The switching transistor is controlled by the precharge signal and a node of the bootstrap capacitor supplying the boosted voltage level is driven high by the switching transistor. A charge on the capacitor represents a 1 bit and the absence worvline a charge represents a 0 bit. The bootstrap unit further includes a load capacitor coupled to the output node.
Also, the wordline voltage woedline circuit enables improved performance without introducing a second power supply, which decreases the system cost. Row decoder circuit for PMOS non-volatile memory cell which uses channel hot electrons for programming. The Output Inverter Stage.
USB1 – Bootstrap circuit – Google Patents
Gate has node 36 as one of its input and turns devices 28 and device 24 off by pulling node to low. One of ordinary skill in the art of integrated circuit design can appreciate the extent of possible electronic design automation tools and applications used in design process without deviating from the scope and spirit of the invention.
The circuit has wordllne capacitor Cb and FETs T1-T7; the interconnection of these components will be explained as the components appear in the description of the operation of the circuit. What is claimed is: The n-channel type field effect transistor Qn61 remains off in so far as the voltage level at the node N31 is constant in either power or ground voltage level, and no current passes through the voltage level adjusting circuit 33b.
Static random access memory sram write assist circuit with leakage suppression and level control. The gate of the FET is connected to a word line. The circuit may also include bootstarp alternately applying the first voltage and then the output potential to an output point for generating pulsating signals of greater amplitude than the magnitude wordoine the applied potential. In the first embodiment of the clock, the gate of a first device is connected to a first node through a second device.
The doubled voltage appears at the other terminal of the capacitor, and this other terminal is connected directly to the circuit output. The features and advantages of the bootstrap circuit according to the present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which:.
The present invention bootsttrap to voltage boosting circuits, and more particularly to a boosting circuit for a wordline clock circuit in a semiconductor memory.
Self wofdline delay circuit and method for compensating sense amplifier clock timing. The low state at node 70 ripples through the inverter chain,, and In the following description, logic “1” level and logic “0” level are assumed to be tantamount to the power voltage level Vcc and the ground voltage level.
US6559707B1 – Bootstrap circuit – Google Patents
In the second embodiment circuit, the load discharges through only one nmos device and consequently discharges faster than the circuit of the first embodiment. As mentioned above, according to the present invention, a bootstrap circuit wordliine constructed to be clamped only at a high potential voltage HVcc and to be normally operated at a low potential voltage source LVcc to easily control on a word line boosting voltage, by sensing the high potential voltage source HVcc and the low potential voltage source LVcc.
One basic difference between the new circuits of the present invention and the prior art, for example the design described in U. Design process may further include, for example, standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, and the like.
Bootstrap circuit for word line driver in semiconductor memory – Etron Technology, Inc.
Initially, the timing signals on leads and are high and the output of the nor gate 58 connected to node 36 is low. Year of fee payment: Capacitive wordlien circuit for the regulation of the word line reading voltage in non-volatile memories. The inverting circuit IN71 shifts a discharging signal CNT4 to the ground voltage level, and the n-channel type field effect transistor Qn71 turns off to block the switching unit 75 from the ground node.
A bootstrap circuit as set boitstrap in claim 2, in which said constant voltage source comprises: The first controlling signal is regulated by the three n-channel type field effect transistors Qn34 to Qn36, and the voltage level of the first wirdline signal is as high as Vcc-3Vthn. Node 36 is connected to the nand gate 60 in two ways, i. The design structure of claim 12wherein the design structure resides on storage medium as a data wodline used for the exchange of layout data of integrated circuits.
A semiconductor integrated circuit for generating an internal supply voltage with reduced voltage swings.